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| M36L0R7060T1 Datasheet, PDF (14/22 Pages) STMicroelectronics – 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package | |||
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Functional description
M36L0R7060T1, M36L0R7060B1
Table 2. Main operating modes(1)
Operation(2)(3) EF GF WF
A0-
LF
RPF WAITF(4) EP CRP GP
WP
LBP,UBP A19 A18
A17
A20-
A21
DQ15-DQ0
Flash Read
VIL VIL VIH VIL(5) VIH
Flash Write
Flash Address
Latch
VIL VIH VIL VIL(5) VIH
VIL X VIH VIL VIH
Flash Output
Disable
VIL VIH VIH X
VIH
Flash Standby VIH X X
Flash Reset X X X
X VIH
X VIL
PSRAM Read
Hi-Z
Hi-Z
Hi-Z
PSRAM Write
PSRAM
Program
Configuration
Register (CR
Controlled)(7)
PSRAM
Standby
PSRAM Deep
Power-Down(9)
The Flash memory must be
disabled.
Any Flash mode is allowed.
PSRAM must be disabled.
Any PSRAM mode is allowed.
VIL VIL VIL VIH VIL
VIL VIL X VIL VIL
Valid
Valid
Flash Data
Out
Flash Data In
Flash Data
Out or Hi-Z(6)
Hi-Z
Hi-Z
Hi-Z
PSRAM data
out
PSRAM data
in
00(RCR) BCR/
VIL VIH X VIL
X 10(BCR) RCR
(8)
Data
Hi-Z
VIH VIL X X
X
XX X
Hi-Z
VIH X X X
X
XX X
Hi-Z
1. X = Don't care.
2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in
Standby and Deep Power-Down modes.
3. The PSRAM must have been configured to operate in asynchronous mode by setting BCR15 to â1â (default value).
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LR128HTB datasheet for
details.
5. LF can be tied to VIH if the valid address has been previously latched.
6. Depends on GF.
7. BCR and RCR only.
8. A18 and A19 are used to select the BCR, RCR or DIDR registers.
9. Bit 4 of the Refresh Configuration Register must be set to â0â and E must be maintained High, VIH, during Deep Power-
Down mode.
14/22
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