M36L0R7060T1 Datasheet, PDF (10/22 Pages) STMicroelectronics – 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package

Signal descriptions
M36L0R7060T1, M36L0R7060B1
2.5
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM
and to the M58LR128HTB datasheet for the Flash memory.
2.6
Flash Chip Enable (E_F)
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component. When Chip Enable is Low, V_IL, and Reset is
High, V_IH, the device is in active mode. When Chip Enable is at V_IH the Flash memory is
deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
2.7
Flash Output Enable (G_F)
The Output Enable pin controls the data outputs during Flash memory Bus Read
operations.
2.8
Flash Write Enable (W_F)
The Write Enable controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9
Flash Write Protect (WP_F)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V_IL, Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at High, V_IH, Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M30L0R7000T1/B1 datasheet).
2.10
Flash Reset (RP_F)
The Reset input provides a hardware reset of the Flash memory. When Reset is at V_IL, the
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I_DD2. Refer to the M58LR128HTB datasheet, for the
value of I_DD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at V_IH, the device is in normal operation. Exiting Reset mode the
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied
to V_RPH (refer to the M58LR128HTB datasheet).
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