M36L0R7060T1 Datasheet, PDF (11/22 Pages) STMicroelectronics – 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package

M36L0R7060T1, M36L0R7060B1
Signal descriptions
2.11
PSRAM Chip Enable input (E_P)
The Chip Enable input activates the PSRAM when driven Low (asserted). When de-
asserted (V_IH), the device is disabled, and goes automatically in low-power Standby mode
or Deep Power-down mode, according to the RCR settings.
2.12
PSRAM Write Enable (W_P)
Write Enable, W_P, controls the Bus Write operation of the PSRAM. When asserted (V_IL), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
PSRAM Output Enable (G_P)
When held Low, V_IL, the Output Enable, G_P, enables the Bus Read operations of the
memory.
2.14
PSRAM Upper Byte Enable (UB_P)
The Upper Byte En-able, UB_P, gates the data on the Upper Byte Data inputs/outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.15
2.16
PSRAM Lower Byte Enable (LB_P)
The Lower Byte Enable, LB_P, gates the data on the Lower Byte Data inputs/outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB_P and UB_P are disabled (High) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as E_P remains Low.
PSRAM Configuration Register Enable (CR_P)
When this signal is driven High, V_IH, bus read or write operations access either the value of
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.17
V_DDF supply voltage
V_DDF provides the power supply to the internal core of the Flash memory. It is the main
power supply for all Flash memory operations (Read, Program and Erase).
2.18
V_CCP supply voltage
V_CCP provides the power supply to the internal core of the PSRAM device. It is the main
power supply for all PSRAM operations.
11/22