PC8374L Datasheet, PDF (92/239 Pages) National Semiconductor (TI) – SensorPathTM SuperI/O with Glue Functions

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4.0 System Wake-Up Control (SWC) (Continued)
4.3.3 SWC Miscellaneous Control Register (SWC_CTL)
This register contains control and status bits for the SWC module. Its reset value depends on the power well of each bit.
Power Well: Varies per bit
Location: Offset 01h
Type:
Varies per bit
Bit
7
6
Name
LOCKSCF Reserved
Reset
0
0
Power Well
V_SB3
5
GOOD_
BAT
0
V_BAT
4
3
Reserved
0
0
2
LAST_PWR
_STATE
0
V_BAT
1
0
LED_OPT
10
V_BAT
Bit Type
Description
7 R/W1S LOCKSCF (Lock SWC Configuration). When set to 1, locks the BLINK and GRN_YLW bits in
SLEDCTL register, and all bits of SWC_CTL, ALEDCTL, LEDBLNK, XLEDCTL, KBDWKCTL, PS2CTL
and PS2KEY0−7 registers by disabling writing to them (including to the LOCKSCF bit itself). Once set,
this bit can be cleared by Hardware reset.
0: R/W bits are enabled for write (default)
1: All bits are RO
6
Reserved.
5
RO GOOD_BAT (Battery Good Status). Indicates the status of the V_BAT backup power. The bit is
powered by the V_BAT backup supply and its value is:
● _{Reset at any time, if VBAT < VBATLOW}
● _{Set when either VDD3 or VSB3 power supply falls below the minimum limit, if VBAT > VBATLOW}
When the bit is ‘0’, the value of the LAST_PWR_STATE bit is incorrect and must be ignored.
0: Backup battery low, or not connected (V_BAT < V_BATLOW)
1: Backup battery good (V_BAT > V_BATLOW)
4-3
Reserved.
2
RO LAST_PWR_STATE (Last Power State). Samples the value of the SLP_S3 signal when a power
failure occurs. It is powered by the V_BAT backup supply, thus preserving its value during a Power Fail
condition (see Section 2.1.2 on page 32). After the AC power returns, reading from this bit returns the
value of the SLP_S3 signal at the time the power failure occurred. The value of this bit must be ignored
when GOOD_BAT bit is 0. Writing to this bit is ignored. At V_BAT Power-Up reset, LAST_PWR_STATE
bit is reset to 0.
0: Orderly system shutdown - Main power off by S3 or S5 sleep states (default)
1: Forced system shutdown - Main power off by Mechanical off (G2 state) or by AC power failure
1-0 R/W or LED_OPT (LED Control Option Select). Selects the Advanced, Standard or Special LED control
RO option for the two power LEDs (yellow and green).
Bits
1 0 LED Control Option
0 0:
03h,
0 1:
1 0:
1 1:
Advanced:
respectively
Standard:
Special:
Reserved
LEDs controlled by the ALEDCTL and LEDBLNK registers at offsets 02h and
LEDs controlled by SLEDCTL register at offset 00h
LEDs controlled by XLEDCTL register at offset 02h (default)
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