PC8374L Datasheet, PDF (46/239 Pages) National Semiconductor (TI) – SensorPathTM SuperI/O with Glue Functions

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3.0 Device Architecture and Configuration (Continued)
Logical Device Memory Map
MEM_BASE+N*400h+Offset
Logical Device N
MEM_BASE+N*400h
Bank 1Fh Registers
3E0h
Bank 1Eh Registers
3C0h
Bank 1Dh Registers
380h
1K
...
Bank 02h Registers
040h
Bank 01h Registers
020h
Bank 00h Registers
32
000h
Figure 7. Logical Device Memory Map with Register Banks
Device Control and
Configuration Registers
MEM_BASE+7C00h
MEM_BASE+7C00h+Offset
PC8374L device Control and
Configuration Registers
3E0h
Logical Device 1E
Configuration Registers
3C0h
Logical Device 1D
Configuration Registers
380h
1K
...
Logical Device 2
Configuration Registers
040h
Logical Device 1
Configuration Registers
020h
Logical Device 0
32
Configuration Registers
000h
Figure 8. Control and Configuration Memory Map
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