PC8374L Datasheet, PDF (90/239 Pages) National Semiconductor (TI) – SensorPathTM SuperI/O with Glue Functions

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4.0 System Wake-Up Control (SWC) (Continued)
4.3 SWC REGISTERS
The offsets of the SWC registers are related to the base address determined by the SWC Base Address register at indexes
60h-61h in the SWC Logical Device configuration.
The following abbreviations are used to indicate the Register Type:
● _{R/W = Read/Write.}
●_R
= Read from register (data written to this address is sent to a different register).
●_W
= Write (see above).
● _RO
● _WO
= Read-only.
= Write-only. Reading from the bit returns 0.
● _{R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.}
● _{R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.}
4.3.1 SWC Register Map
The following table lists the SWC registers. For the SWC register bitmap, see Section 4.5 on page 107. The SWC registers
are V_SB3 powered.
Table 36. SWC Register Map
Offset
Option¹
Mnemonic
Register Name
LED_OPT = 01 SLEDCTL Standard LED Control
00h
LED_OPT = other Reserved
01h
SWC_CTL SWC Miscellaneous Control
LED_OPT = 00 ALEDCTL Advanced LED Control
02h LED_OPT = 10 XLEDCTL Special LED Control
LED_OPT = other Reserved
LED_OPT = 00 LEDBLNK LED Blinking Control
03h
LED_OPT = other Reserved
04h
KBDWKCTL Keyboard Wake-Up Control
05h
PS2CTL
PS2 Protocol Control
06h
KDSR
Keyboard Data Shift-Register
07h
MDSR
Mouse Data Shift-Register
08h
PS2KEY0 PS2 Keyboard Key Data 0
09h
PS2KEY1 PS2 Keyboard Key Data 1
0Ah
PS2KEY2 PS2 Keyboard Key Data 2
0Bh
PS2KEY3 PS2 Keyboard Key Data 3
0Ch
PS2KEY4 PS2 Keyboard Key Data 4
0Dh
PS2KEY5 PS2 Keyboard Key Data 5
0Eh
PS2KEY6 PS2 Keyboard Key Data 6
0Fh
PS2KEY7 PS2 Keyboard Key Data 7
1. Selected by LED_OPT field in SWC_CTL register.
Type Power Well Section
R/W or RO
V_SB3
4.3.2
Varies per bit Varies per bit
R/W or RO
V_SB3
R/W or RO
V_DD3
4.3.3
4.3.4
4.3.5
R/W or RO
V_SB3
4.3.6
R/W or RO
R/W or RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
V_SB3
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.11
4.3.11
4.3.11
4.3.11
4.3.11
4.3.11
4.3.11
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