DS92LV1224 Datasheet, PDF (9/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

AC Timing Diagrams and Test Circuits (Continued)
Timing shown for RCLK_R/F = LOW
Duty Cycle (t_RDC) =
20138713
FIGURE 6. Deserializer Data Valid Out Times
FIGURE 7. Deserializer TRI-STATE Test Circuit and Timing
20138714
9
www.national.com