DS92LV1224 Datasheet, PDF (1/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

April 2005
DS92LV1224
30-66 MHz 10 Bit Bus LVDS Deserializer
General Description
The DS92LV1224 is a 300 to 660 Mb/s deserializer for
high-speed unidirectional serial data transmission over FR-4
printed circuit board backplanes and balanced copper
cables. It receives the Bus LVDS serial data stream from a
compatible 10–bit serializer, transforms it back into a 10-bit
wide parallel data bus and recovers parallel clock. This
single serial data stream simplifies PCB design and reduces
PCB cost by narrowing data paths that in turn reduce PCB
size and number of layers. The single serial data stream also
reduces cable size, the number of connectors, and elimi-
nates clock-to-data and data-to-data skew.
The DS92LV1224 works well with any National Semiconduc-
tor’s Bus LVDS 10–bit serializer within its specified fre-
quency operating range. It features low power consumption,
and high impedance outputs in power down mode.
The DS92LV1224 was designed with the flow-through pinout
and is available in a space saving 28–lead SSOP package.
Features
n 30–66 MHz Single 1:10 Deserializer with 300–660 Mb/s
troughput
n Robust Bus LVDS serial data transmission with
embedded clock with embedded clock for exceptional
noise immunity and low EMI
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
n Low power consumption < 300 mW (typ) @ 66 MHz
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Small 28-lead SSOP package
Block Diagrams
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