DS92LV1224 Datasheet, PDF (6/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_RFCP
t_RFDC
t_RFCP /
t_TCP
t_RFTT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK
REFCLK Transition Time
15.15
T
30
50
95
1
3
Max
33.33
70
105
6
Units
ns
%
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions Pin/Freq.
Min
Typ
t_RCP
Receiver out Clock
Period
t_RCP = t_TCP
RCLK
15.15
Rout(0-9),
CMOS/TTL Low-to-High
t_CLH
Transition Time
CL = 15 pF
LOCK,
RCLK
1.2
Figure 3
CMOS/TTL High-to-Low
t_CHL
Transition Time
1.1
All Temp./
All Freq.
1.75*t_RCP+1.25 1.75*t_RCP+3.75
Deserializer Delay
t_DD
Figure 5
Room
Temp./
3.3V/30MHz
Room
Temp./
3.3V/40MHz
1.75*t_RCP+2.25 1.75*t_RCP+3.75
1.75*t_RCP+2.25 1.75*t_RCP+3.75
Room
Temp./
3.3V/66MHz
1.75*t_RCP+2.75 1.75*t_RCP+3.75
RCLK
30MHz
0.4*t_RCP
0.5*t_RCP
t_ROS
ROUT Data Valid
before RCLK
Figure 6
RCLK
40MHz
0.4*t_RCP
0.5*t_RCP
RCLK
66MHz
0.38*t_RCP
0.5*t_RCP
t_ROH
ROUT Data valid after
RCLK
Figure 6
t_RDC
t_HZR
RCLK Duty Cycle
HIGH to TRI-STATE
Delay
30MHz
40MHz
66MHz
−0.4*t_RCP
−0.4*t_RCP
−0.38*t_RCP
45
−0.5*t_RCP
−0.5*t_RCP
−0.5*t_RCP
50
2.8
t_LZR
LOW to TRI-STATE
2.8
Delay
Figure 7
Rout(0-9)
t_ZHR TRI-STATE to HIGH
4.2
Delay
t_ZLR
TRI-STATE to LOW
4.2
Delay
Deserializer PLL Lock
30MHz
1.68
t_DSR1
time from PWRDWN
(with SYNCPAT)
40MHz
66MHz
1.31
0.84
Max
33.33
4
4
1.75*t_RCP+6.25
1.75*t_RCP+5.25
1.75*t_RCP+5.25
1.75*t_RCP+4.75
55
10
10
10
10
3
3
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
µs
µs
µs
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