DS92LV1224 Datasheet, PDF (11/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

AC Timing Diagrams and Test Circuits (Continued)
SW - Setup and Hold Time (Internal Data Sampling Window)
t_DJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
t_RNM = Receiver Noise Margin Time
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FIGURE 10. Receiver Bus LVDS Input Skew Margin
Deserializer Truth Table
INPUTS
OUTPUTS
PWRDN
REN
ROUT [0:9]
LOCK
RCLK
H
H
Z
H
Z
H
H
Active
L
Active
L
X
Z
Z
Z
H
L
Z
Active
Z
1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
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