DS92LV1224 Datasheet, PDF (14/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

Pin Diagrams
20138717
FIGURE 13. Random Lock Hot Insertion
DS92LV1224TMSA - Deserializer
20138719
Deserializer Pin Description
Pin Name
ROUT
RCLK_R/F
I/O
No.
O
15–19, 24–28
I
2
RI+
RI−
PWRDN
I
5
I
6
I
7
LOCK
O
10
RCLK
REN
O
9
I
8
Description
Data Output. ±9 mA CMOS level outputs.
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the PLL
and TRI-STATEs outputs putting the device into a low power sleep
mode.
LOCK goes low when the Deserializer PLL locks onto the embedded
clock edge. CMOS level output. Totem pole output structure, does
not directly support wire OR connection.
Recovered Clock. Parallel data rate clock recovered from embedded
clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9, LOCK
and RCLK when driven low.
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