DS92LV1224 Datasheet, PDF (10/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

AC Timing Diagrams and Test Circuits (Continued)
FIGURE 8. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
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FIGURE 9. Deserializer PLL Lock Time from SyncPAT
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