DS92LV1224 Datasheet, PDF (7/16 Pages) National Semiconductor (TI) – 30-66 MHz 10 Bit Bus LVDS Deserializer

Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions Pin/Freq.
Min
Typ
t_DSR2
Deserializer PLL Lock
time from SYNCPAT
30MHz
40MHz
66MHz
0.62
0.47
0.29
TRI-STATE to HIGH
t_{ZHLK Delay (power-up)}
LOCK
3.7
30 MHz
650
950
Deserializer Noise
Figure 10
t_RNM
Margin
40 MHz
450
730
(Note 7)
66 MHz
250
400
Max
Units
1
µs
1
µs
0.8
µs
12
ns
ps
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical
Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device
pins is defined as negative. Voltages are referenced to ground except VOD,
∆VOD, VTH and VTL which are differential voltages.
Note 4: t_LLHT and t_LHLT specifications are Guranteed By Design (GBD)
using statistical analysis.
Note 5: Because the Serializer is in TRI-STATE mode, the Deserializer will
lose PLL lock and have to resynchronize before data transfer.
Note 6: For the purpose of specifying deserializer PLL performance, tDSR1
and tDSR2 are specified with the REFCLK running and stable, and with
specific conditions for the incoming data stream (SYNCPATs). It is recom-
mended that the derserializer be initialized using either t_DSR1 timing or t_DSR2
timing. t_DSR1 is the time required for the deserializer to indicate lock upon
power-up or when leaving the power-down mode. Synchronization patterns
should be sent to the device before initiating either condition. t_DSR2 is the time
required to indicate lock for the powered-up and enabled deserializer when
the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
Note 7: t_RNM is a measure of how much phase noise (jitter) the deserializer
can tolerate in the incoming data stream before bit errors occur. The Dese-
rializer Noise Margin is Guaranteed By Design (GBD) using statistical
analysis.
AC Timing Diagrams and Test Circuits
FIGURE 2. “Worst Case” Deserializer ICC Test Pattern
20138704
20138706
FIGURE 3. Deserializer CMOS/TTL Output Load and Transition Times
7
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