DS90CP04_07 Datasheet, PDF (8/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4x4 LVDS Crosspoint Switch

Symbol
Parameter
Conditions
Typ (Note
Min
2)
Max
T_DCCLK
CSCLK Duty Cycle
Input SCLK Duty Cycle set at 50%
45
55
RSCLK Duty Cycle
t_S
SI–SCLK or MODE–SCLK Setup From SI or MODE Input Data to SCLK _1.5
Time
Rising Edge
t_H
SCLK–SI or SCLK–MODE Hold From SCLK Rising Edge to SI or
1
Time
MODE Input Data
t_DSO
SCLK to RSO or CSO Delay
From SCLK to RSO or CSO
1.5
4
t_DSCLK
SCLK to RSCLK or CSCLK Delay From SCLK to RSCLK or CSCLK
4.0
8.5
t_DSDIF
|SCLK to RSCLK or CSCLK–
SCLK to RSO or CSO|
Propagation Delay Difference
between t_DSO and t_DSCLK
1.5
4.5
T_RISE
Logic Low to High Transition Time 20% to 80% at RSO, CSO, RSCLK,
1.5
or CSCLK
T_FALL
Logic High to Low Transition Time 80% to 20% at RSO, CSO, RSCLK,
or CSCLK
1.5
Units
%
ns
ns
ns
ns
ns
ns
ns
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters are measured at V_DD = 2.5V, T_A = 25°C. They are for reference purposes, and are not production-tested.
Note 3: Differential output voltage V_OD is defined as |OUT+–OUT−|. Differential input voltage V_ID is defined as |IN+–IN−|.
Note 4: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 5: Characterized from any input to any one differential LVDS output running at the specified data rate and data pattern, with all other 3 channels running
K28.5 pattern at 1.25 Gb/s asynchronously to the channel under test. Jitter is not production-tested, but guaranteed through characterization on sample basis.
Random Jitter is measured peak to peak with a histogram including 1000 histogram window hits. K28.5 pattern is repeating bit streams of (0011111010
1100000101). This deterministic jitter or DJ pattern is measured to a histogram mean with a sample size of 350 hits. Like RJ the Total Jitter or TJ is measured
peak to peak with a histogram including 3500 window hits.
FIGURE 2. Differential Driver DC Test Circuit
20028712
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