DS90CP04_07 Datasheet, PDF (7/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4x4 LVDS Crosspoint Switch

Symbol
Parameter
Conditions
Typ (Note
Min
2)
Max
I_OZ
Output TRI-STATE Current
TRI-STATE Output
V_OUT = V_DD or V_SS
−10
+10
I_OFF
Power Off Leakage Current
V_DD = 0V, V_OUT = 2.5V or GND
−10
+10
I_OS
Output Short Circuit Current, One OUT+ or OUT− Short to GND
Complementary Output
OUT+ or OUT− Short to V_DD
−15
-40
15
40
I_OSB
Output Short Circuit Current, both OUT+ and OUT− Short to GND
Complementary Outputs
OUT+ and OUT− Short to V_CM
−15
-30
15
30
C_OUT2
Output Capacitance
OUT+ or OUT− to GND when TRI-
STATE
5.5
SUPPLY CURRENT
I_CCD
Total Supply Current
All inputs and outputs enabled,
terminated with differential load of
220
300
100Ω between OUT+ and OUT-.
I_CCZ
TRI-STATE Supply Current
TRI-STATE All Outputs
SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figures 3, 5, 6)
10
20
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at
Time
200 Mb/s, measure between 20%
100
135
160
t_HLT
Differential High to Low Transition ^{and 80% of V}OD^.
Time
100
135
160
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at
500
200 Mb/s, measure at 50% V_OD
between input to output.
500
750
1200
750
1200
t_SKD1
t_SKCC
Pulse Skew
|t_PLHD–t_PHLD|
Output Channel to Channel Skew Difference in propagation delay
(t_PLHD or t_PHLD) among all output
0
channels in Broadcast mode (any one
input to all outputs).
0
30
50
100
t_JIT
Jitter (Note 5)
Alternating 1 and 0 Pattern
750 MHz
1.25 GHz
K28.5 Pattern
1.5 Gb/s
2.5 Gb/s
PRBS 2²³-1 Pattern
1.5 Gb/s
2.5 Gb/s
t_ON
LVDS Output Enable Time
Time from LOAD = LH or SELx to
OUT± change from TRI-STATE to
50
active.
t_OFF
LVDS Output Disable Time
Time from LOAD = LH or SELx to
OUT± change from active to TRI-
STATE.
t_SW
LVDS Switching Time
Time from LOAD = LH to new switch
configuration effective for OUT±.
t_SEL
SELx to OUT±
Configuration select to new data at
OUT±.
SWITCHING CHARACTERISTICS — Serial control Interface (Figures 4, 8, 9)
F_SCLK
SCLK Clock Frequency
0
1.6
2.5
1.6
2.5
10
40
27
60
25
40
40
70
150
300
3
5
50
150
50
150
100
Units
µA
µA
mA
mA
mA
mA
pF
mA
mA
ps
ps
ps
ps
ps
ps
psrms
psrms
psp-p
psp-p
psp-p
psp-p
ns
ns
ns
ns
MHz
7
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