DS90CP04_07 Datasheet, PDF (13/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4x4 LVDS Crosspoint Switch

MSB
LSB OUT1± Connects to
OUT2± Connects to
OUT3± Connects to
1
0
1 Invalid.
1
1
0 Use of these invalid combinations may cause loss of synchronization.
1
1
1
OUT4± Connects to
Row and Column Addressing
The upper left device in an array of NxN devices is assigned
row address 0, and column address 0. The devices to its right
have column addresses of 1 to N, whereas devices below it
have row addresses of 1 to N. The Serial Control Interface
(SCLK and SI) is connected to the first device with the row
and column addresses of 0. The Serial Control Interface shifts
in a control word containing the row and column address of
the device it wants to access. When the control data propa-
gates through each device, the control word's address is
internally decremented by one before it is sent to the next row
or column device. When the control data is sent out the col-
umn interface (CSO and CSCLK) the row address is decre-
mented by one. Similarly, when the column address data is
shifted out the row interface (RSO and RSCLK) the column
address is decremented by one. By the time the control word
reaches the device it has been intended to program, both the
row and column addresses have been decremented to 0.
Each device constantly checks for the receipt of a frame start
(D29-24=01 1111'b or 01 1110'b). When it detects the proper
start frame string, and the row and column addresses it re-
ceives are both 0, the device responds by storing the switch
configuration data of the 30-bit control word into its load reg-
ister.
Each device in the array is sequentially programmed through
the serial interface. When programming is completed for the
entire array, LOAD is pulsed high and the load register's con-
tent is transferred to the configuration register of each device.
The LOAD pulse must wait until the final bit of the control word
has been placed into the "load" register. This timing is guar-
anteed to take place two clock cycles after programming has
been completed.
Due to internal shift registers additional SCLK cycles will be
necessary to complete array programming. It takes 7 clock
(SCLK) positive edge transitions for the control data to appear
at RSO and CSO for its near neighbor. Users must provide
the correct number of clock transitions for the control data
word to reach its destination in the array. Table 3 shows an
example of the control data words for a 4 device serial chain
with connections (OUT1=IN1, OUT2=IN2, OUT16=IN16). To
program the array, it requires four 30-bit control words to rip-
ple through the serial chain and reach their destinations. In
order to completely program the array in the 120 clock cycles
associated with the 30-bit control words it is important to pro-
gram the last device in the chain first. The following program-
ming data pushes the initial data through the chain into the
correct devices.
Read-Back Switch Configuration
The DS90CP04 is put into read-back mode by sending a spe-
cial “Read” start frame (01 1110'b). Upon receipt of the special
read start frame the configuration register information is trans-
ferred into the shift register and output at both RSO and CSO
in the OUT1 to OUT4 bit segments of the read control word.
Each time the read-back data from a device passes through
its downstream device, its default address (11 1111'b) is in-
ternally decremented by one. The “relative” column address
emerges at RSO of the last device in the row and is used to
determine (11 1111'b - N) the column of the sending device.
Similarly, the row address emerges at CSO of the sending
device. After inserting the channel configuration information
in the “read” control word, the device will automatically revert
to write mode, ready to accept a new control word at SI.
Table 4 shows an example of reading back the configuration
registers of 4 devices in the first row of a 4x4 device array.
Again, due to internal shift registers additional SCLK cycles
will be necessary to complete the array read. It takes 4x30
SCLK clock cycles to shift out 4 30-bit configuration registers
plus 7 SCLK cycles per device to account for device latency
making for a total SCLK count of 148. The serialized read data
is sampled at RSO and synchronized with RSCLK of the last
device in the row. The user is recommended to backfill with
all 0's at SI after the four reads have been shifted in.
TABLE 3. Example to Program a 4 Device Array
Frame
D29:D24
Row
Address
D23:D18
Column
Address
D17:D12
OUT1
D11:D9
OUT2
D8:D6
OUT3
D5:D3
OUT4
D2:D0
01 1111
00 0000
00 0011
001
010
011
100
01 1111
00 0000
00 0010
001
010
011
100
01 1111
00 0000
00 0001
001
010
011
100
01 1111
00 0000
00 0000
001
010
011
100
Shift in configuration information from device furthest from system SI input first to minimize array
latency during the programming process.
The 2 clock cycle delay ensures all channel information has reached the “load” register and all switches
are ready to be configured.
Number of
SCLK
Cycles
30
30
30
30
2
Control Word
Destination
Device in Array
Row, Column
0, 3
0, 2
0, 1
0, 0
13
www.national.com