DS90CP04_07 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4x4 LVDS Crosspoint Switch

Pin Descriptions
Pin
Name
Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN1+
IN1−
16
I, LVDS
Inverting and non-inverting differential inputs.
15
IN2+
IN2−
14
I, LVDS
Inverting and non-inverting differential inputs.
13
IN3+
IN3−
12
I, LVDS
Inverting and non-inverting differential inputs.
11
IN4+
IN4−
10
I, LVDS
Inverting and non-inverting differential inputs.
9
SWITCHED DIFFERENTIAL OUTPUTS
OUT1+
25
OUT1−
26
O, LVDS
Inverting and non-inverting differential outputs. OUT1± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4±
OUT2+
27
OUT2−
28
O, LVDS
Inverting and non-inverting differential outputs. OUT2± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4±
OUT3+
29
OUT3−
30
O, LVDS
Inverting and non-inverting differential outputs. OUT3± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4
OUT4+
31
OUT4−
32
O, LVDS
Inverting and non-inverting differential outputs. OUT4± can be connected to any one pair
IN1±, IN2±, IN3±, or IN4±
DIGITAL CONTROL INTERFACE
SCLK
6
I, LVCMOS Control clock to latch in programming data at SI. SCLK can be 0 MHz to 100 MHz. SCLK
should be burst of clock pulses active only while accessing the device. After completion
of programming, SCLK should be kept at logic low to minimize potential noise injection
into the high-speed differential data paths.
SI / SEL1
7
I, LVCMOS
Programming data to select the switch configuration. Data is latched into the input buffer
register at the rising edge of SCLK.
SEL0
5
I, LVCMOS Programming data to select the switch configuration.
CSO
RSO
18
O, LVCMOS With MODE low, control data is shifted out at CSO (RSO) for cascading to the next device
2
in the serial chain. The control data at CSO (RSO) is identical to that shifted in at SI with
the exception of the device column (row) address being decremented by one internally
before propagating to the next device in the chain. CSO (RSO) is clocked out at the rising
edge of SCLK.
CSCLK
RSCLK
19
O, LVCMOS With MODE low, these pins function as a buffered control clock from SCLK. CSCLK
3
(RSCLK) is used for cascading the serial control bus to the next device in the serial chain.
LOAD
22
I, LVCMOS When LOAD is high and SCLK makes a LH transition, the device transfers the
programming data in the load register into the configuration registers. The new switch
configuration for all outputs takes effect. LOAD needs to remain high for only one SCLK
cycle to complete the process, holding LOAD high longer repeats the transfer to the
configuration register.
MODE
23
I, LVCMOS When MODE is low, the SCLK is active and a buffered SCLK signal is present at the
CLKOUT output. When MODE is high, the SCLK signal is uncoupled from register and
state machine internals. Internal registers will see an active low signal until MODE is
brought Low again.
POWER
V_DD
GND
1, 8, 17, 24
4, 20, 21,
DAP
I, Power
I, Power
V_DD = 2.5V ±5%. At least 4 low ESR 0.01 µF bypass capacitors should be connected from
V_DD to GND plane.
Ground reference to LVDS and CMOS circuitry.
DAP is the exposed metal contact at the bottom of the LPP-32 package. The DAP is used
as the primary GND connection to the device. It should be connected to the ground plane
with at least 4 vias for optimal AC and thermal performance.
3
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