DS90CP04_07 Datasheet, PDF (4/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4x4 LVDS Crosspoint Switch

Serial Interface Truth Table
LOAD
0
0
LH
1
MODE
0
1
0
1
SCLK
LH
LH
X
LH
Resulting Action
The current state on SI is clocked into the input shift register.
Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and
CSCLK outputs will drive an active Low signal until MODE is brought Low again. See
Configuration Select Truth Table below.
Loads OUT1–OUT4 configuration information from last valid frame. Places contents of load
register into the configuration register. The switch configuration is updated asynchronously
from the SCLK input.
Uncouples SCLK input from internal registers and state machine inputs. The RSCLK and
CSCLK outputs will drive an active Low signal until MODE is brought Low again. See
Configuration Select Truth Table below.
Configuration Select Truth Table
MODE
0
1
1
1
1
SEL1
X
0
0
1
1
SEL0
X
0
1
0
1
LH: Low to High (positive edge) transition.
X: Don't Care or Not Applicable.
Resulting Action
The SEL0/1 pins only function in configuration select mode. See below.
Distribution: IN1 - OUT1 OUT2 OUT3 OUT4
Distribution: IN2 - OUT1 OUT2 OUT3 OUT4
Redundancy: IN1 - OUT1 OUT2 and IN3 - OUT3 OUT4
Broadside: IN1 - OUT1, IN2 - OUT2, IN3 - OUT3, IN4 - OUT4
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