DS90CP04_07 Datasheet, PDF (14/18 Pages) National Semiconductor (TI) – 1.5 Gbps 4x4 LVDS Crosspoint Switch

Frame
D29:D24
01 1110
01 1110
01 1110
01 1110
Row
Address
D23:D18
00 0000
00 0000
00 0000
00 0000
TABLE 4. A Read-Back Example from a 4 Device Array
Column
Address
D17:D12
OUT1
D11:D9
OUT2
D8:D6
OUT3
D5:D3
OUT4
D2:D0
11 1111
000
000
000
000
11 1110
000
000
000
000
11 1101
000
000
000
000
11 1100
001
010
011
100
Number of
SCLK
Cycles
30
30
30
30
Descriptions
Read-Back
(R,C)=0, 3
Read-Back
(R,C)=0, 2
Read-Back
(R,C)=0, 1
Read-Back
(R,C)=0, 0
Note 7: LOAD and READ programming example is based on the 16x16 array configuration shown in Figure 11. Alternative expansion array configurations will
require a slightly different programming sequence.
Switch Expansion For Minimum Programming Latency
driven by the same “load” signal. To prevent excessive stub
Programming data ripples through the array through RSO and
RSCLK in the row and CSO and CSCLK in the first column.
LOAD pins of all devices are electrically tied together and
length in the array from affecting the signal quality of LOAD,
it is recommended that the load signal is distributed to each
row or column in large crosspoint array applications.
FIGURE 11.
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