PC87307 Datasheet, PDF (7/218 Pages) National Semiconductor (TI) – PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

Table of Contents
4.5 APC REGISTERS ...................................................................................................................... 60
4.5.1 APC Control Register 1 (APCR1), Index 40h .............................................................. 60
4.5.2 APC Control Register 2 (APCR2), Index 41h .............................................................. 61
4.5.3 APC Status Register (APSR), Index 42h ..................................................................... 61
4.5.4 RAM Lock Register (RLR), Index 47h ......................................................................... 62
4.6 RTC AND APC REGISTER BITMAPS ...................................................................................... 62
4.6.1 RTC Register Bitmaps ................................................................................................. 62
4.6.2 APC Register Bitmaps ................................................................................................. 63
4.7 REGISTER BANK TABLES ....................................................................................................... 64
5.0 _{The Digital Floppy Disk Controller (FDC) (Logical Device 3)}
5.1 FDC FUNCTIONS ..................................................................................................................... 66
5.1.1 Microprocessor Interface ............................................................................................. 66
5.1.2 System Operation Modes ............................................................................................ 66
5.2 DATA TRANSFER ..................................................................................................................... 67
5.2.1 Data Rates ................................................................................................................... 67
5.2.2 The Data Separator ..................................................................................................... 67
5.2.3 Perpendicular Recording Mode Support ..................................................................... 68
5.2.4 Data Rate Selection ..................................................................................................... 68
5.2.5 Write Precompensation ............................................................................................... 69
5.2.6 FDC Low-Power Mode Logic ....................................................................................... 69
5.2.7 Reset ........................................................................................................................... 69
5.3 THE REGISTERS OF THE FDC ............................................................................................... 70
5.3.1 Status Register A (SRA), Offset 00h ........................................................................... 70
5.3.2 Status Register B (SRB), Offset 01h ........................................................................... 71
5.3.3 Digital Output Register (DOR), Offset 02h .................................................................. 71
5.3.4 Tape Drive Register (TDR), Offset 03h ....................................................................... 73
5.3.5 Main Status Register (MSR), Offset 04h, Read Operations ........................................ 74
5.3.6 Data Rate Select Register (DSR), Offset 04h, Write Operations ................................ 75
5.3.7 Data Register (FIFO), Offset 05h ................................................................................ 76
5.3.8 Digital Input Register (DIR), Offset 07h, Read Operations .......................................... 77
5.3.9 Configuration Control Register (CCR), Offset 07h, Write Operations ......................... 78
5.4 THE PHASES OF FDC COMMANDS ....................................................................................... 78
5.4.1 Command Phase ......................................................................................................... 78
5.4.2 Execution Phase .......................................................................................................... 78
5.4.3 Result Phase ............................................................................................................... 80
5.4.4 Idle Phase .................................................................................................................... 80
5.4.5 Drive Polling Phase ..................................................................................................... 80
5.5 THE RESULT PHASE STATUS REGISTERS .......................................................................... 81
5.5.1 Result Phase Status Register 0 (ST0) ......................................................................... 81
5.5.2 Result Phase Status Register 1 (ST1) ......................................................................... 81
5.5.3 Result Phase Status Register 2 (ST2) ......................................................................... 82
5.5.4 Result Phase Status Register 3 (ST3) ......................................................................... 83
5.6 FDC REGISTER BITMAPS ....................................................................................................... 84
5.6.1 FDC Standard Register Bitmaps ................................................................................. 84
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