PC87307 Datasheet, PDF (141/218 Pages) National Semiconductor (TI) – PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

UART1 and UART2 (with IR) (Logical Devices 5 and 6)
7.11.1 Receiver Data Port (RXD) or the Transmitter
Data Port (TXD), Bank 0, Offset 00h
These ports share the same address.
RXD is accessed during CPU read cycles. It is used to read
data from the Receiver Holding Register when the FIFOs
are disabled, or from the bottom of the RX_FIFO when the
FIFOs are enabled. See Figure 7-3.
TXD is accessed during CPU write cycles. It is used to write
data to the Transmitter Holding Register when the FIFOs
are disabled, or to the TX_FIFO when the FIFOs are en-
abled. See Figure 7-4.
DMA cycles always access the TXD and RXD ports, regard-
less of the selected bank.
Receiver Data Port (RXD), Bank 0, Offset 00h
76543210
Receiver Data
Reset
Port (RXD)
Bank 0,
Required
Offset 00h
Received Data
FIGURE 7-3. RXD Register Bitmap
Bits 7-0 - Received Data
Used to access the Receiver Holding Register when the
FIFOs are disabled, or the bottom of the RX_FIFO when
the FIFOs are enabled.
Transmitter Data Port (TXD), Bank 0, Offset 00h
76543210
Transmitter Data
Reset
Port (TXD)
Bank 0,
Required
Offset 00h
7.11.2 Interrupt Enable Register (IER), Bank 0,
Offset 01h
This register controls the enabling of various interrupts.
Some interrupts are common to all operating modes of the
module, while others are mode specific. Bits 4 to 7 can be
set in Extended mode only. They are cleared in Non-Ex-
tended mode. The bits of the Interrupt Enable Register
(IER) are defined differently, depending on the operating
mode of the module.
The different modes can be divided into the following four
groups:
• Non-Extended (which includes UART, Sharp-IR and
SIR).
• UART and Sharp-IR in Extended mode.
• SIR in Extended mode.
• Consumer-IR.
The following sections describe the bits in this register for
each of these modes.
The reset mode for the IER is the Non-Extended UART
mode.
When edge-sensitive interrupt triggers are employed, user
is advised to clear all IER bits immediately upon entering
the interrupt service routine and to re-enable them prior to
exiting (or alternatively, to disable CPU interrupts and re-
enable prior to exiting). This will guarantee proper interrupt
triggering in the interrupt controller in case one or more in-
terrupt events occur during execution of the interrupt rou-
tine.
If the LSR, MSR or EIR registers are to be polled, interrupt
sources which are identified by self-clearing bits should
have their corresponding IER bits set to 0, to prevent spuri-
ous pulses on the interrupt output pin.
If an interrupt source must be disabled, the CPU can do so
by clearing the corresponding bit in the IER register. How-
ever, if an interrupt event occurs just before the correspond-
ing enable bit in the IER register is cleared, a spurious
interrupt may be generated. To avoid this problem, the
clearing of any IER bit should be done during execution of
the interrupt service routine. If the interrupt controller is pro-
grammed for level-sensitive interrupts, the clearing of IER
bits can also be performed outside the interrupt service rou-
tine, but with the CPU interrupt disabled.
Transmitted Data
FIGURE 7-4. TXD Register Bitmap
Bits 7-0 - Transmitted Data
Used to access the Transmitter Holding Register when
the FIFOs are disabled or the top of TX_FIFO when the
FIFOs are enabled.
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