PC87307 Datasheet, PDF (145/218 Pages) National Semiconductor (TI) – PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

UART1 and UART2 (with IR) (Logical Devices 5 and 6)
TABLE 7-4. Modem Status Event Detection Enable
IRMSSL Value
Bit Function
0
Modem Status Event (MS_EV)
1
Forced to 0.
Bit 4 - DMA Event Occurred (DMA_EV)
When an 8237 type DMA controller is used, this bit is set
to 1 when a DMA terminal count (TC) is signalled. It is
cleared upon read.
Bit 5 - Transmitter Empty (TXEMP_EV)
In UART, Sharp-IR and Consumer-IR modes, this bit is
the same as bit 6 of the LSR register. It is set to 1 when
the transmitter is empty.
Bits 7,6 - Reserved
Read/Write 0.
7.11.4 FIFO Control Register (FCR), Bank 0, Offset
02h
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
Write Cycles
76543210
FIFO Control
0 0 0 0 0 0 0 0 Reset
Register (FCR)
Bank 0,
0
Required
Offset 02h
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
FIGURE 7-10. FCR Register Bitmap
Bit 0 - FIFO Enable (FIFO_EN)
When set to 1 enables both the Transmision and Recep-
tion FIFOs. Resetting this bit clears both FIFOs.
In Consumer-IR modes the FIFOs are always enabled
and the setting of this bit is ignored.
Bit 1 - Receiver Soft Reset (RXSR)
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
Bit 2 - Transmitter Soft Reset (TXSR)
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Bit 3 - Reserved
Read/Write 0.
Writing to this bit has no effect on the UART operation.
Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
In Non-Extended modes, these bits have no effect.
In Extended modes, these bits select the TX_FIFO in-
terrupt threshold level. An interrupt is generated when
the level of the data in the TX_FIFO drops below the en-
coded threshold.
TABLE 7-5. TX_FIFO Level Selection
TXFTH (Bits 5,4)
TX_FIF0 Tresh.
(16 Levels)
TX_FIF0 Tresh.
(32 Levels)
00(Default)
1
1
01
3
7
10
9
17
11
13
25
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded thresh-
old.
TABLE 7-6. RX_FIFO Level Selection
RXFTH (Bits 5,4)
RX_FIF0 Tresh.
(16 Levels)
RX_FIF0 Tresh.
(32 Levels)
00(Default)
1
1
01
4
8
10
8
16
11
14
26
7.11.5 Link Control Register (LCR), Bank 0, Offset
03h, and Bank Selection Register (BSR),
All Banks, Offset 03h
The Link Control Register (LCR) and the Bank Select Reg-
ister (BSR) (see the next register) share the same address.
The Link Control Register (LCR) selects the communica-
tions format for data transfers in UART, SIR and Sharp-IR
modes.
Upon reset, all bits are set to 0.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Link Control Register (SH_LCR) register in
bank 3 (See Section 7.13.2 on page 157). During a write op-
eration to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
• If bit 7 is 0, the write affects both LCR and BSR.
• If bit 7 is 1, and it is not one of the codes that selects
bank 1 (see Table 7-9, “Bank Selection Encoding” on
page 147), the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
Upon reset, all bits are set to 0.
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