PC87307 Datasheet, PDF (133/218 Pages) National Semiconductor (TI) – PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

Parallel Port (Logical Device 4)
Bits 7-5 of ECR = 111
7 6 5 4 3 2 1 0 _{Configuration Register B}
0 0 0 0 0 0 0 0 Reset
(CNFGB)
Offset 401h
Required
DMA Channel Select
Reserved
Interrupt Select
IRQ Signal Value
Reserved
7
6
5
4
3
2
1
0
ECP Extended Auxiliary
Status Register (EAR)
0 0 0 0 0 0 0 0 Reset
Offset 405h
Required
Reserved
FIFO Tag
76543210
Extended Control
0 0 0 1 0 1 0 1 Reset
(ECR)
Offset 402h
Required
FIFO Empty
FIFO Full
ECP Interrupt Service
ECP DMA Enable
ECP Interrupt Mask
ECP Mode Control
76543210
Control0 Register
0 0 0 0 0 0 0 0 Reset
Second Level
Offset 00h
Required
EPP Time-Out
Interrupt Mask
Reserved
Reserved
Reserved
Freeze Bit
DCR Register Live
Reserved
7 6 5 4 3 2 1 0 _{ECP Extended Index}
0 0 0 0 0 0 0 0 Reset
Register (EIR)
Offset 403h
Required
Second Level Offset
Reserved
Reserved
Reserved
Reserved
Reserved
76543210
Control2 Register
0 0 0 0 0 0 0 0 Reset
Second Level
Offset 02h
Required
Reserved
Reserved
Reserved
EPP 1.7 ZWS Control
Revision 1.7 or 1.9 Select
Reserved
Channel Address Enable
SPP Compatibility
76543210
ECP Extended Data
0 0 0 0 0 0 0 0 Reset
Register (EDR)
Offset 404h
Required
D0
D1
D2
D3
D4
D5
Data Bits
D6
D7
76543210
Control4 Register
0 0 0 0 0 1 1 1 Reset
Second Level
Offset 04h
Required
PP DMA Request
Active Time
Reserved
PP DMA Request Inactive Time
Reserved
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