PC87307 Datasheet, PDF (124/218 Pages) National Semiconductor (TI) – PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

Parallel Port (Logical Device 4)
Bits 1,0 - DMA Channel Select
These bits reflect the value of bits 1,0 of the PP Config0
register (second level offset 05h). Microsoft’s ECP Pro-
tocol and ISA Interface Standard defines these bits as
shown in Table 6-7.
Bits 1,0 of PP Config0 are read/write bits, but CNFGB
bits are read only.
Upon reset, these bits are initialized to 00.
TABLE 6-7. ECP Mode DMA Selection
Bit 1 Bit 0
DMA Configuration
0 0 8-bit DMA selected by jumpers. (Default)
01
DMA channel 1 selected.
10
DMA channel 2 selected.
11
DMA channel 3 selected.
Bit 2 - Reserved
This bit is reserved and is always 0.
Bits 5-3 - Interrupt Select Bits
These bits reflect the value of bits 5-3 of the PP Config0
register at second level index 05h. Microsoft’s ECP Pro-
tocol and ISA Interface Standard defines these bits as
shown in Table 6-8.
Bits 5-3 of PP Config0 are read/write bits, but CNFGB
bits are read only.
Upon reset, these bits have undefined values.
TABLE 6-8. ECP Mode Interrupt Selection
Bit 5 Bit 4 Bit 3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt Selection
Selected by jumpers.
IRQ7 selected.
IRQ9 selected.
IRQ10 selected.
IRQ11 selected.
IRQ14 selected.
IRQ15 selected.
IRQ5 selected.
Bit 6 - IRQ Signal Value
This bit holds the value of the IRQ signal configured by
the Interrupt Select register (index 70h of this logical de-
vice).
Bit 7 - Reserved
This bit is reserved and is always 0.
6.5.12 Extended Control Register (ECR), Offset 402h
This register controls the ECP and parallel port functions.
On reset this register is initialized to 00010101. IOCHRDY
is driven low on an ECR read when the ECR status bits do
not hold updated data.
76543210
Extended Control
0 0 0 1 0 1 0 1 Reset
Register (ECR)
Offset 402h
Required
FIFO Empty
FIFO Full
ECP Interrupt Service
ECP DMA Enable
ECP Interrupt Mask
ECP Mode Control
FIGURE 6-26. ECR Register Bitmap
Bit 0 - FIFO Empty
This bit continuously reflects the FIFO state, and there-
fore can only be read. Data written to this bit is ignored.
When the ECP clock is frozen this bit is read as 1, re-
gardless of the actual FIFO state.
0 - The FIFO has at least one byte of data.
1 - The FIFO is empty or ECP clock is frozen.
Bit 1 - FIFO Full
This bit continuously reflects the FIFO state, and there-
fore can only be read. Data written to this bit is ignored.
When the ECP clock is frozen this bit is read as 1, re-
gardless of the actual FIFO state.
0 - The FIFO has at least one free byte.
1 - The FIFO is full or ECP clock frozen.
Bit 2 - ECP Interrupt Service
This bit enables servicing of interrupt requests. It is set
to 1 upon reset, and by the occurrence of interrupt
events. It is set to 0 by software.
While this bit is 1, neither the DMA nor the interrupt
events listed below will generate an interrupt.
While this bit is 0, the interrupt setup is “armed” and an
interrupt is generated on occurrence of an interrupt
event.
While the ECP clock is frozen, this bit always returns a
0 value, although it retains its proper value and may be
modified.
When one of the following interrupt events occurs while
this bit is 0, an interrupt is generated and this bit is set
to 1 by hardware.
— DMA is enabled (bit 3 of ECR is 1) and terminal
count is reached.
— FIFO write threshold reached (no DMA - bit 3 of ECR
is 0; forward direction (bit 5 of DCR is 0), and there
are eight or more bytes free in the FIFO).
— FIFO read threshold reached (no DMA - bit 3 of ECR
is 0; read direction set - bit 5 of DCR is 1, and there
are eight or more bytes to read from the FIFO).
0 - The DMA and the above interrupts are not disabled.
1 - The DMA and the above three interrupts are disabled.
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