PC87307 Datasheet, PDF (26/218 Pages) National Semiconductor (TI) – PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O

Configuration
TABLE 2-4. Parallel Port Address Range Allocation
Parallel Port Mode
SuperI/O Parallel Port
Configuration Register Bits
7654
Decoded Range ^a
SPP
00xx
Three registers, from base to base + 02h
EPP (Non ECP Mode 4)
01xx
Eight registers, from base to base + 07h
ECP, No Mode 4,
No Internal Configuration
1000
Six registers, from base to base + 02h and
from base + 400h to base + 402h
ECP with Mode 4,
No Internal Configuration
1110
11 registers, from base to base + 07h and
from base + 400h to base + 402h
ECP with Mode 4,
Configuration within Parallel Port
1001
or
1111
16 registers, from base to base + 07h and
from base + 400h to base + 407h
a. The SuperI/O processor does not decode the Parallel Port outside this range.
2.3 THE CONFIGURATION REGISTERS
The configuration registers control the setup of the part.
Their major functions are to:
• Identify the chip
• Enable major functions (such as, the Keyboard Control-
ler (KBC) for the keyboard and the mouse, the Real-
Time Clock (RTC), including Advanced Power Control
(APC), the Floppy Disc Controller (FDC), UARTs, paral-
lel and general purpose ports, power management and
pin functionality)
• Define the I/O addresses of these functions
• Define the status of these functions upon reset
Section 2.3.2 summarizes information for each register of
each function. In addition, the following non-standard, or
card control registers are described in detail in Section 2.4,
starting on page 34.
• Card Control Registers
— SuperI/O Configuration 1 Register (SIOC1)
— SuperI/O Configuration 2 Register (SIOC2)
— Programmable Chip Select Configuration Index
Register
— Programmable Chip Select Configuration Data Reg-
ister
• KBC Configuration Register (Logical Device 0)
— SuperI/O KBC Configuration Register
• FDC Configuration Registers (Logical Device 3)
— SuperI/O FDC Configuration Register
— Drive ID Register
• Parallel Port Configuration Register (Logical Device 4)
— SuperI/O Parallel Port Configuration Register
• UART2 and Infrared Configuration Register (Logical
Device 5)
— SuperI/O UART2 Configuration Register
• UART1 Configuration Register (Logical Device 6)
— SuperI/O UART1 Configuration Register
• Programmable Chip Select Configuration Registers
— CS0 Base Address MSB Register
— CS0 Base Address LSB Register
— CS0 Configuration Register
— CS1 Base Address MSB Register
— CS1 Base Address LSB Register
— CS1 Configuration Register
— CS2 Base Address MSB Register
— CS2 Base Address LSB Register
— CS2 Configuration Register
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