DS90CR561 Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

AC Timing Diagrams (Continued)
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Note 7: The worst case test pattern produces a maximum toggling of device digital circuitry, LVDS I/O and TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figure 1 and Figure 2 show a rising edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
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FIGURE 3. DS90CR561 (Transmitter) LVDS Output Load and Transition Timing
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FIGURE 4. DS90CR562 (Receiver) CMOS/TTL Output Load and Transition Timing
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FIGURE 5. DS90CR561 (Transmitter) Input Clock Transition Time
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