DS90CR561 Datasheet, PDF (11/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

DS90CR561 Pin Description — FPD Link Transmitter (Continued)
Pin Name
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
I4
I5
I1
I2
I1
I3
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
Description
DS90CR562 Pin Description — FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
I3
I3
O 21
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The rising edge acts as data strobe.
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state.
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
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