DS90CR561 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TPDD Transmitter Powerdown Delay (Figure 15)
Note 5: This limit based on bench characterization.
Min Typ Max Units
100
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RCOP
RSKM
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4)
CMOS/TTL High-to-Low Transition Time (Figure 4)
RxCLK OUT Period (Figure 8)
Receiver Skew Margin (Note 6)
f = 20 MHz
V_CC = 5V, T_A = 25˚C (Figure 18)
RxCLK OUT High Time (Figure 8)
f = 40 MHz
f = 20 MHz
f = 40 MHz
RxCLK OUT Low Time (Figure 8)
f = 20 MHz
f = 40 MHz
RxCLK Setup to RxCLK OUT (Figure 8)
f = 20 MHz
f = 40 MHz
RxCLK Hold to RxCLK OUT (Figure 8)
f = 20 MHz
f = 40 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C,
V_CC = 5.0V (Figure 10)
Receiver Phase Lock Loop Set (Figure 12)
Receiver Powerdown Delay (Figure 16)
Min
Typ
Max
Units
3.5
6.5
ns
2.7
6.5
ns
25
T
50
ns
1.1
ns
700
ps
19
ns
6
ns
21.5
ns
10.5
ns
14
ns
4.5
ns
16
ns
6
ns
7.6
11.9
ns
10
ms
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependant on the type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012470-5
5
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