DS90CR561 Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TRANSMITTER SUPPLY CURRENT
I_CCTZ
Transmitter Supply Current,
Power Down
RECEIVER SUPPLY CURRENT
I_CCRW Receiver Supply Current,
Worst Case
I_CCRG Receiver Supply Current,
16 Grayscale
I_CCRZ
Receiver Supply Current,
Power Down
Conditions
Power Down = Low
Min Typ Max Units
1 25 µA
C_L = 8 pF,
Worst Case Pattern (Figures 1, 4)
C_L = 8 pF,
16 Grayscale Pattern (Figures 2, 4)
Power Down = Low
f = 32.5 MHz
f = 37.5 MHz
f = 32.5 MHz
f = 37.5 MHz
55 75 mA
60 80 mA
35 55 mA
37 58 mA
1 10 µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 5.0V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_OD and ∆V_OD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V _CC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
LLHT
LVDS Low-to-High Transition Time (Figure 3 )
LHLT
LVDS High-to-Low Transition Time (Figure 3 )
TCIT
TxCLK IN Transition Time (Figure 5)
TCCS TxOUT Channel-to-Channel Skew (Note 5) (Figure 6)
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 17)
f = 20 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 17)
f = 40 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TCIP
TxCLK IN Period (Figure 7)
TCIH
TxCLK IN High Time (Figure 7)
TCIL
TxCLK IN Low Time (Figure 7)
TSTC TxIN Setup to TxCLK IN (Figure 7)
f = 20 MHz
f = 40 MHz
THTC TxIN Hold to TxCLK IN (Figure 7)
TCCD TxCLK IN to TxCLK OUT Delay @ 25˚C,
TPLLS
V_CC = 5.0V (Figure 9)
Transmitter Phase Lock Loop Set (Figure 11)
Min
−200
6.3
12.8
20
27.2
34.5
42.2
−100
2.9
6.1
9.7
13
17
20.3
25
0.35T
0.35T
14
8
2.5
5
Typ
0.75
0.75
150
7.2
13.6
20.8
28
35.2
42.6
100
3.3
6.6
10.2
13.5
17.4
20.8
T
0.5T
0.5T
2
Max
1.5
1.5
8
350
350
7.5
14.6
21.5
28.5
35.6
42.9
300
3.9
7.1
10.7
14.1
17.8
21.4
50
0.65T
0.65T
9.7
10
Units
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
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