DS90CR561 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

July 1997
DS90CR561/DS90CR562
LVDS 18-Bit Color Flat Panel Display (FPD) Link
General Description
The DS90CR561 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR562 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE, FP-
FRAME, DRDY) are transmitted at a rate of 280 Mbps per
LVDS data channel. Using a 40 MHz clock, the data through-
put is 105 Megabytes per second. These devices are offered
with rising edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n Up to 105 Megabyte/sec bandwidth
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design
n Power-down mode
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
Block Diagrams
DS90CR561
DS90CR562
DS012470-27
Order Number DS90CR561MTD
See NS Package Number MTD48
Order Number DS90CR562MTD
See NS Package Number MTD48
DS012470-1
APPLICATION
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© 1998 National Semiconductor Corporation DS012470
DS012470-2
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