DS90CR561 Datasheet, PDF (10/12 Pages) National Semiconductor (TI) – LVDS 18-Bit Color Flat Panel Display (FPD) Link

AC Timing Diagrams (Continued)
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
DS012470-25
DS012470-26
SW — Setup and Hold Time (Internal data sampling window)
TCCS — Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — Typically 10 ps–40 ps per foot
FIGURE 18. Receiver LVDS Input Skew Margin
DS90CR561 Pin Description — FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
I/O No.
I 21
O3
O3
I1
O1
O1
I1
Description
TTL Level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines (FPLINE,
FPFRAME, DRDY). (Also referred to as HSYNC, VSYNC and DATA ENABLE.)
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The rising edge acts as data strobe.
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
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