PC87364 Datasheet, PDF (57/180 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support

2.0 Device Architecture and Configuration (Continued)
2.10.4 Drive ID Register
This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in the Enhanced
mode.
Location: Index F1h
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
Drive 1 ID
Drive 0 ID
0
0
0
0
0
0
0
0
Bit
Description
7-4 Reserved
3-2 Drive 1 ID. When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.
1-0 Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.
Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register
in the Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support
automatic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 respectively (to indicate non-valid media
sense) when the corresponding drive is selected and the Drive ID bit is reflected on bit 5 of the TDR register in the Enhanced
mode.
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