PC87364 Datasheet, PDF (145/180 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support

8.0 ACCESS.bus Interface (ACB) (Continued)
8.3.3 ACB Status Register (ACBST)
This register maintains the current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h).
Location: Offset 01h
Type:
Varies per bit
Bit
Name
Reset
7
SLVSTP
0
6
SDAST
0
5
BER
0
4
NEGACK
0
3
STASTR
0
2
NMATCH
0
1
MASTER
0
0
XMIT
0
Bit Type
Description
7 R/W1C SLVSTP (Slave Stop). Writing 0 to SLVSTP is ignored.
0: Writing 1 or ACB disabled
1: Stop Condition detected after a slave transfer in which MATCH or GCMATCH was set
6 RO SDAST (SDA Status)
0: Reading from the ACBSDA register during a receive, or when writing to it during a transmit. When
ACBCTL1.START is set, reading the ACBSDA register does not clear SDAST. This enables ACB to
send a repeated start in master receive mode.
1: SDA Data register awaiting data (transmit - master or slave) or holds data that should be read
(receive - master or slave).
5 R/W1C BER (Bus Error). Writing 0 to BER is ignored.
0: Writing 1 or ACB disabled
1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer
of bits 2 through 8 and acknowledge cycle), or when an arbitration problem is detected.
4 R/W1C NEGACK (Negative Acknowledge). Writing 0 to NEGACK is ignored.
0: Writing 1 or ACB disabled
1: Transmission not acknowledged on the ninth clock (In this case, SDAST is not set)
3 R/W1C STASTR (Stall After Start). Writing 0 to STASTR is ignored.
0: Writing 1 or ACB disabled
1: Address sent successfully (i.e., a Start Condition sent without a bus error, or Negative Acknowledge),
if ACBCTL1.STASTRE is set. This bit is ignored in slave mode. When STASTR is set, it stalls the
ACCESS.bus by pulling down the SCL line, and suspends any further action on the bus (e.g., receive
of first byte in master receive mode). In addition, if ACBCTL1.INTEN is set, it also causes the ACB
to send an interrupt.
2 R/W1C NMATCH (New Match). Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent
when this bit is set.
0: Software writes 1 to this bit
1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match.
1 RO Master
0: Arbitration loss (BER is set) or recognition of a Stop Condition
1: Bus master request succeeded and master mode active
0 RO XMIT (Transmit). Direction bit.
0: Master/slave transmit mode not active
1: Master/slave transmit mode active
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