PC87364 Datasheet, PDF (159/180 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support

9.0 Legacy Functional Blocks (Continued)
Table 54. Bank 2 Register Map
Offset
00h
01h
02h
03h
04h
05h
06h
07h
Mnemonic
Register Name
BGD(L) Baud Generator Divisor Port (Low Byte)
BGD(H) Baud Generator Divisor Port (High Byte)
EXCR1 Extended Control1
LCR/BSR Line Control/Bank Select
EXCR2 Extended Control 2
Reserved
TXFLV TX_FIFO Level
RXFLV RX_FIFO Level
Table 55. Bank 3 Register Map
Offset Mnemonic
Register Name
00h
01h
02h
03h
04h-07h
MRID Module Revision ID
SH_LCR Shadow of LCR (Read Only)
SH_FCR Shadow of FIFO Control (Read Only)
LCR/BSR Line Control/Bank Select
Reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
RO
RO
RO
R/W
157
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