PC87364 Datasheet, PDF (42/180 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support

2.0 Device Architecture and Configuration (Continued)
2.6 LED OPERATION AND STATES
The device supports up to two LEDs, depending on Pin 25 and Pin 26 Function Select (bits 1-2 and bit 3) of the SIOCFA
register. The polarity of both LEDs is determined by LED Polarity Control (bit 7) of the SIOCFD register.
, when in power-on state. The device also provides modes for hardware LED control. This enables the LEDs to support fea-
tures such as power and error indication.
The LEDs may be operated in software, hardware1 or hardware 2 modes. These modes are set by LED Mode Control (bits
2 and 3) of the SIOCFB register. Each LED can be set to On, Off or to blink at different rates by means of bits 0-2 (LED1)
and bits 3-5 (LED2) of the SIOCFC register. When in power-on state (both V_DD and V_SB exist), the LEDs are software-con-
trolled. When in power fail state (no V_SB and no V_DD) the LEDs are off. Table 14 shows the effect of hardware modes 1 and
2 on LED operation that override the above rules.
Table 14. Hardware Modes 1 and 2 Effect on LED Operation
Mode
System State
LED1
Hardware 1
(SIOCFB, bits 3-2=01)
Hardware 2
(SIOCFB, bits 3-2=10)
V_SB power-up reset
Off
Power off (V_SB, no V_DD) Software-controlled
ACPI mode and
Sleep State 3
Software-controlled
ACPI mode, Sleep State 5,
bit 6 = 1 in SIOCFC register
and Power Supply Control
Software-controlled
enabled
ACPI mode, any other
configuration
Off
Legacy mode and power off
(no V_DD)
Off
LED2
1 Hz blink, 50% duty cycle
1 Hz blink, 50% duty cycle
Software-controlled
Software-controlled
Off
Off
2.7 POWER SUPPLY CONTROL AND LED CONFIGURATION
A combination of two strap pins (Power Supply and LED Configuration 0 and 1, PSLDC0,1, pins 99 and 107 respectively)
determines the configuration of the power supply control pins and LEDs. Both pins 99 and 107 have weak pull-downs, and
are sampled on V_SB power-up reset. Table 15 describes how they affect the chip configuration.
Table 15. PSLDC0,1 Configuration Options
PSLDC0
(Pin 99)
0
0
1
1
PSLDC1
(Pin 107)
0
1
0
1
Power Supply Control
LED2
Enabled (default)
Disabled
Disabled
Enabled
Not selected (default)
Selected
Not selected
Selected
2.8 REGISTER TYPE ABBREVIATIONS
The following abbreviations are used to indicate the Register Type:
q _{R/W = Read/Write}
q _{R = Read from a specific address returns the value of a specific register. Write to the same address is to a different}
register.
q _{W = Write}
q _{RO = Read Only}
q _{R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.}
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