PC87364 Datasheet, PDF (177/180 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support

10.0 Device Characteristics (Continued)
10.4.10 Standard Parallel Port Timing
Symbol
Parameter
t_PDH Port Data Hold
t_PDS Port Data Setup
t_SW
Strobe Width
Conditions
Typ
These times are system dependent 500
and are therefore not tested.
These times are system dependent 500
and are therefore not tested.
These times are system dependent 500
and are therefore not tested.
Max Unit
ns
ns
ns
BUSY
Typical Data Exchange
ACK
PD7-0
STB
t_PDS
t_SW
t_PDH
10.4.11 Enhanced Parallel Port Timing
Symbol
t_WW19a
t_WW19ia
t_WST19a
t_WEST
t_WPDH
t_WPDS
t_EPDW
t_EPDH
Parameter
Min
WRITE Active from WAIT Low
WRITE Inactive from WAIT Low
DSTRB or ASTRB Active from WAIT Low
DSTRB or ASTRB Active after WRITE Active 10
PD7-0 Hold after WRITE Inactive
0
PD7-0 Valid after WRITE Active
PD7-0 Valid Width
80
PD7-0 Hold after DSTRB or ASTRB Inactive 0
Max EPP 1.7 EPP 1.9 Unit
45
ns
45
ns
65
ns
ns
ns
15
ns
ns
ns
WRITE
DSTRB
or
ASTRB
PD7-0
WAIT
t_WW19a
t_WST19a
t_WEST
t_WPDS
t_WPDH
t_WW19ia
t_WST19a
t_EPDH
Valid
t_EPDW
175
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