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HPC16064 Datasheet, PDF (5/36 Pages) National Semiconductor (TI) – High-Performance microController
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5 ) VCC 5V g10% unless otherwise specified TA 0 C to a70 C for
HPC46064 46004 b40 C to a85 C for HPC36064 36004 b40 C to a105 C for HPC26064 26004 b55 C to a125 C for
HPC16064 16004
Symbol and Formula
Parameter
Min Max Units Notes
fC
tC1 1 fC
tCKIH
tCKIL
tC 2 fC
tWAIT tC
tDC1C2R
tDC1C2F
fU fC 8
fMW
fXIN fC 22
tXIN tC
CKI Operating Frequency
2
CKI Clock Period
33
CKI High Time
15
CKI Low Time
16 6
CPU Timing Cycle
66
CPU Wait State Period
66
Delay of CK2 Rising Edge after CKI Falling Edge
0
Delay of CK2 Falling Edge after CKI Falling Edge
0
External UART Clock Input Frequency
External MICROWIRE PLUS Clock Input Frequency
External Timer Input Frequency
Pulse Width for Timer Inputs
66
30
500
55
55
3 75
1 875
1 36
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
(Note 2)
(Note 2)
tUWS
MICROWIRE Setup Time
Master
Slave
100
20
ns
tUWH
MICROWIRE Hold Time
Master
Slave
20
50
ns
tUWV
MICROWIRE Output Valid Time
Master
Slave
50
150
ns
tSALE
tC a 40
tHWP tC a 10
tHAE tC a 85
tHAD
tC a 85
tBF
tC a 66
tBE
tC a 66
tUAS
tUAH
tRPW
tOE
tOD
tDRDY
tWDW
tUDS
tUDH
tA
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
90
76
151
135
99
99
10
10
100
0
60
5
35
70
40
10
20
70
ns
ns
ns
(Note 3)
ns
ns
(Note 5)
ns
(Note 5)
ns
ns
ns
ns
ns
(Note 6)
ns
ns
ns
ns
ns
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
5