HPC16064 Datasheet, PDF (24/36 Pages) National Semiconductor (TI) – High-Performance microController

Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows the
HPC46064 to be used as an intelligent peripheral to another
processor The UPI could thus be used to tightly link two
HPC46064’s and set up systems with very high data ex-
change rates Another area of application could be where
an HPC46064 is programmed as an intelligent peripheral to
a host system such as the Series 32000 microprocessor
Figure 27 illustrates how an HPC46064 could be used as an
intelligent peripherial for a Series 32000-based application
The interface consists of a Data Bus (port A) a Read Strobe
(URD) a Write Strobe (UWR) a Read Ready Line (RDRDY)
a Write Ready Line (WRRDY) and one Address Input (UA0)
The data bus can be either eight or sixteen bits wide
The URD and UWR inputs may be used to interrupt the
HPC46064 The RDRDY and WRRDY outputs may be used
to interrupt the host processor
The UPI contains an Input Buffer (IBUF) an Output Buffer
(OBUF) and a Control Register (UPIC) In the UPI mode
port A on the HPC46064 is the data bus UPI can only be
used if the HPC46064 is in the Single-Chip mode
FIGURE 27 HPC46064 as a Peripheral (UPI Interface to Series 32000 Application)
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