HPC16064 Datasheet, PDF (3/36 Pages) National Semiconductor (TI) – High-Performance microController

20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5 ) V_CC 5V g10% T_A 0 C to a70 C for HPC46064 46004 b40 C to
a85 C for HPC36064 36004 b40 C to a105 C for HPC26064 26004 b55 C to a125 C for HPC16064 16004
Symbol and Formula
Parameter
Min Max Units
Notes
f_C
t_C1 1 f_C
t_CKIH
t_CKIL
t_C 2 f_C
t_WAIT t_C
t_DC1C2R
t_DC1C2F
f_U f_C 8
f_MW
f_XIN f_C 22
t_XIN t_C
CKI Operating Frequency
CKI Clock Period
CKI High Time
CKI Low Time
CPU Timing Cycle
CPU Wait State Period
Delay of CK2 Rising Edge 2fter CKI Falling Edge
Delay of CK2 Falling Edge after CKI Falling Edge
External UART Clock Input Frequency
External MICROWIRE PLUS Clock Input Frequency
External Timer Input Frequency
Pulse Width for Timer Inputs
2
20
50
500
22 5
22 5
100
100
0
55
0
55
25
1 25
0 91
100
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
(Note 2)
(Note 2)
t_UWS
MICROWIRE Setup Time
Master
Slave
100
20
ns
t_UWH
MICROWIRE Hold Time
Master
Slave
20
50
ns
t_UWV
MICROWIRE Output Valid Time
Master
Slave
50
150
ns
t_SALE
t_C a 40
t_HWP t_C a 10
t_HAE t_C a 100
t_HAD
t_C a 85
t_BF
t_C a 66
t_BE
t_C a 66
t_UAS
t_UAH
t_RPW
t_OE
t_OD
t_DRDY
t_WDW
t_UDS
t_UDH
t_A
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
115
ns
110
ns
200
ns
(Note 3)
160
ns
116
ns
(Note 5)
116
ns
(Note 5)
10
ns
10
ns
100
ns
0
60
ns
5
35
ns
(Note 6)
70
ns
40
ns
10
ns
20
ns
70
ns
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
3