HPC16064 Datasheet, PDF (4/36 Pages) National Semiconductor (TI) – High-Performance microController

20 MHz (Continued)
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5 ) V_CC 5V g10% T_A 0 C to a70 C for HPC46064 46004 b40 C to
a85 C for HPC36064 36004 b40 C to a105 C for HPC26064 26004 b55 C to a125 C for HPC16064 16004
Symbol and Formula
Parameter
Min Max Units
Notes
t_DC1ALER
Delay from CKI Rising Edge to
ALE Rising Edge
0
35
ns
(Notes 1 2)
t_DC1ALEF
Delay from CKI Rising Edge to
ALE Falling Edge
0
35
ns
(Notes 1 2)
t_DC2ALER
t_C a 20
Delay from CK2 Rising Edge to
ALE Rising Edge
45
ns
(Note 2)
t_DC2ALEF
t_C a 20
Delay from CK2 Falling Edge to
ALE Falling Edge
45
ns
(Note 2)
t_LL
t_C b 9
t_ST
t_C b 7
ALE Pulse Width
Setup of Address Valid before
ALE Falling Edge
41
ns
18
ns
t_VP
t_C b 5
Hold of Address Valid after
ALE Falling Edge
20
ns
t_ARR
t_C b 5
ALE Falling Edge to RD Falling Edge
20
ns
t_ACC t_C a WS b 55
Data Input Valid after Address Output Valid
145
ns
t_RD
t_C a WS b 65
Data Input Valid after RD Falling Edge
85
ns
t_RW
t_C a WS b 10
RD Pulse Width
140
ns
t_DR
t_C b 15
Hold of Data Input Valid after
RD Rising Edge
0
60
ns
(Note 6)
t_RDA t_C b 15
Bus Enable after RD Rising Edge
85
ns
t_ARW
t_C b 5
ALE Falling Edge to WR Falling Edge
45
ns
t_WW
t_C a WS b 15 WR Pulse Width
160
ns
t_V
t_C a WS b 5
Data Output Valid before WR Rising Edge
145
ns
t_HW
t_C b 5
Hold of Data Valid after WR Rising Edge
20
ns
t_DAR
t_C a WS b 50
Falling Edge of ALE to
Falling Edge of RDY
75
ns
t_RWP t_C
RDY Pulse Width
100
ns
Note C_L 40 pF
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t_CKIR and t_CKIL) on CKI input less than 2 5 ns
Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 t_HAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later t_HAE may be as long as (3 t_C a 4WS a 72 t_C a 100) may occur depending on the following CPU instruction cycles its wait states and ready
input
Note 4 WS (t_WAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency t_C 20 MHz with
one wait state programmed
Note 5 Due to emulation restrictions actual limits will be better
Note 6 This is guaranteed by design and not tested
4