DS64BR401 Datasheet, PDF (5/30 Pages) National Semiconductor (TI) – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Pin Name
Pin Number I/O, Type
Pin Descriptions
Control Pins — Both Modes (LVCMOS)
RATE
21
I, Float,
RATE, 3–level controls the pulse width of de-emphasis of the
LVCMOS
output.
RATE = 0 forces 3 Gbps,
RATE = 1 forces 6 Gbps,
RATE = Float enables auto rate detection and the pulse width
(pull-back) is set appropriately after each exit from IDLE. This
requires the transition from IDLE to ACTIVE state — OOB
signal. See Table 2
TXIDLEA,TXIDLEB 24, 25
I, Float,
LVCMOS
TXIDLEA/B, 3–level controls the driver output.
TXIDLEA/B = 0 disables the signal detect/squelch function for
all A/B outputs.
TXIDLEA/B = 1 forces the outputs to be muted (electrical idle).
TXIDLEA/B = Float enables the signal auto detect/squelch
function and the signal detect voltage threshold level can be
adjusted using the SD_TH pin. See Table 3
VOD0, VOD1
22, 23
I, LVCMOS w/ VOD[1:0] adjusts the output differential amplitude voltage
internal pull- level.
down
VOD[1:0] = 00 sets output VOD = 600 mV (Default)
VOD[1:0] = 01 sets output VOD = 800 mV
VOD[1:0] = 10 sets output VOD = 1000 mV
VOD[1:0] = 11 sets output VOD = 1200 mV
PWDN
52
I, LVCMOS PWDN = 0 enables the device (normal operation).
PWDN = 1 disables the device (low power mode).
Pin must be driven to a logic low at all time or normal operation
is not guaranteed.
Analog
SD_TH
27
I, ANALOG Threshold select pin for electrical idle detect threshold. Float
pin for typical default 130 mVp-p (differential), otherwise
connect resistor from SD_TH to GND to set threshold voltage.
See Table 4, Figure 5
Power
VDD
9, 14, 36, 41, Power
51
Power supply pins. 2.5 V +/-5%
GND
DAP
Power
DAP is the large metal contact at the bottom side, located at
the center of the 54 pin LLP package. It should be connected
to the GND plane with at least 4 via to lower the ground
impedance and improve the thermal performance of the
package.
NC
26
No Connect — Leave pin open
1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
Don't drive FLOAT pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
5
www.national.com