DS64BR401 Datasheet, PDF (26/30 Pages) National Semiconductor (TI) – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Applications Information
GENERAL RECOMMENDATIONS
The DS64BR401 is a high performance circuit capable of de-
livering excellent performance. Careful attention must be paid
to the details associated with high-speed design as well as
providing a clean power supply. Refer to the LVDS Owner's
Manual for more detailed information on high speed design
tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and LPDS outputs must have a controlled
differential impedance of 100Ω. It is preferable to route dif-
ferential lines exclusively on one layer of the board, particu-
larly for the input traces. The use of vias should be avoided if
possible. If vias must be used, they should be used sparingly
and must be placed symmetrically for each side of a given
differential pair. Route the differential signals away from other
signals and noise sources on the printed circuit board. See
AN-1187 for additional information on LLP packages.
The graphic shown below depicts a typical microstrip trace
routing design of the top and bottom layers. This should be
used as a reference to achieve the optimal system perfor-
mance. Impedance discontinuities at the differential via can
be minimized or eliminated by increasing the swell around
each via hole. To further improve the signal quality, a ground
via placed close to the signal via for a low inductance return
current path is recommended. When the via structure is as-
sociated with stripline trace and a thick board, further opti-
mization such as back drilling is often used to reduce the high
frequency effects of via stubs on the signal path. To minimize
cross-talk coupling, it is recommended to have >3X gap spac-
ing between the differential pairs. For example, if the trace
width is 5 mils with 5 mils spacing – 100Ω differential
impedance (closely coupled). The gap spacing between the
differential pairs should be >15 mils.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS64BR401 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the V_DD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01 μF bypass ca-
pacitor should be connected to each V_DD pin such that the
capacitor is placed as close as possible to the DS64BR401.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic.
FIGURE 7. Typical PCB Trace Routing
300730101
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