DS64BR401 Datasheet, PDF (16/30 Pages) National Semiconductor (TI) – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Below are examples to configure the device and bring the in-
ternal IDLE and RATE status to pins 19, 20, 46, 47.
To monitor the IDLE detect with two channels ORed (CH0
with CH2, CH1 with CH3, CH4 with CH6, CH5 with CH7):
Write 32'h to address 0x47.
The following IDLE status should be observable on the ex-
ternal pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means IDLE is detected (no signal
present).
Pin = LOW (GND) means ACTIVE (data signal present).
To monitor the RATE detect with two channels ORed (CH0
with CH2, CH1 with CH3, CH4 with CH6, CH5 with CH7):
Write C0'h to address 0x4C.
The following RATE status should be observable on the ex-
ternal pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means high data rate is detected (6 Gbps).
Pin = LOW (GND) means low rate is detected (3 Gbps).
TABLE 5. SMBus Register Map
Address Register Name
0x00
Reset
Bit (s) Field
7:2 Reserve
1
Block SMBus Reset
0x01
0
Reset
PWDN Channels 7:0 PWDN CHx
0x02
0x08
PWDN Control
7:1 Reserve
0
Override PWDN
Pin Control Override 7:5
4
Reserve
Override IDLE
3
Reserve
2
Override RATE
1:0 Reserve
Type Default
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
Description
Set bits to 0.
SMBus Reset Block
0: Allow SMBus reset from bit 0
1: Block SMBus reset from bit 0
SMBus Reset
1: Reset registers to default value
Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
Set bits to 0.
0: Allow PWDN pin control
1: Block PWDN pin control
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
0: Allow RATE pin control
1: Block RATE pin control
Set bits to 0.
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