DS64BR401 Datasheet, PDF (4/30 Pages) National Semiconductor (TI) – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Pin Descriptions
Pin Name
Pin Number I/O, Type Pin Descriptions
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10, 11
12, 13
15, 16
17, 18
I, CML
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INA_n+ to VDD and INA_n- to VDD when enabled.
OA_0+, OA_0-,
OA_1+, OA_1-,
OA_2+, OA_2-,
OA_3+, OA_3-
35, 34
33, 32
31, 30
29, 28
O, LPDS
Inverting and non-inverting low power differential signaling
(LPDS) 50Ω outputs with de-emphasis. Compatible with AC
coupled CML inputs.
IB_0+, IB_0- ,
IB_1+, IB_1-,
IB_2+, IB_2-,
IB_3+, IB_3-
45, 44
43, 42
40, 39
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the
equalizer. A gated on-chip 50Ω termination resistor connects
INB_n+ to VDD and INB_n- to VDD when enabled.
OB_0+, OB_0-,
1, 2
OB_1+, OB_1-,
3, 4
OB_2+, OB_2-,
5, 6
OB_3+, OB_3-
7, 8
O, LPDS
Inverting and non-inverting low power differential signaling
(LPDS) 50Ω outputs with de-emphasis. Compatible with AC
coupled CML inputs.
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal pull- When pulled high provide access internal digital registers that
down
are a means of auxiliary control for such functions as
equalization, de-emphasis, VOD, rate, and idle detection
threshold.
When pulled low, access to the SMBus registers are disabled
and SMBus function pins are used to control the Equalizer
and De-Emphasis.
Please refer to “SMBus configuration Registers” section and
Electrical Characteristics - Serial Management Bus Interface
for detail information.
ENSMB = 1 (SMBUS MODE)
SDA, SCL
49, 50
I, LVCMOS
ENSMB = 1
The SMBus SDA (data input/output bi-directional) and SCL
(clock input) pins are enabled.
AD[3:0]
46, 47, 53, 54
I, LVCMOS w/ ENSMB = 1
internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are
down
the user set SMBus slave address inputs. See section —
System Management Bus (SMBus) and Configuration
Registers for additional information.
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I, Float,
LVCMOS
EQA/B, 3–level controls the level of equalization of the A/B
sides. The EQA/B pins are active only when ENSMB is de-
asserted (Low). Each of the 4 A/B channels have the same
level unless controlled by the SMBus control registers. When
ENSMB goes high the SMBus registers provide independent
control of each lane. See Table 1
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I, Float,
LVCMOS
DEMA/B, 3–level controls the level of de-emphasis of the A/
B sides. The DEMA/B pins are only active when ENSMB is
de-asserted (Low). Each of the 4 A/B channels have the same
level unless controlled by the SMBus control registers. When
ENSMB goes High the SMBus registers provide independent
control of each lane. See Table 2
www.national.com
4