DS64BR401 Datasheet, PDF (25/30 Pages) National Semiconductor (TI) – Quad Bi-Directional Transceiver with Equalization and De-Emphasis

Address Register Name
0x47
EN
Digital Test Point
IDLE Detect
0x4C
EN
Digital Test Point
RATE Detect
0x4E
Digital Test
Bit (s) Field
Type Default
7:6 Reserve
R/W 0x02
5
CH2, CH3 CH6, CH7
4
CH0, CH1 CH4, CH5
3:0 Reserve
7
CH2, CH3 CH6, CH7 R/W 0x00
6
CH0, CH1 CH4, CH5
5:0 Reserve
7:1 Reserve
R/W 0x00
0
Block AD[3:0] pins
Description
Set bits to 0.
0: Disabled IDLE Test Point for CH2, 3, 6, 7.
1: Enable IDLE Test Point for CH2, 3, 6, 7.
0: Disabled IDLE Test Point for CH0, 1, 4, 5.
1: Enable IDLE Test Point for CH0, 1, 4, 5.
Set bits to 0010'b or h'2.
0: Disabled RATE Test Point for CH2, 3, 6, 7.
1: Enable RATE Test Point for CH2, 3, 6, 7.
0: Disabled RATE Test Point for CH0, 1, 4, 5.
1: Enable RATE Test Point for CH0, 1, 4, 5.
Set bits to 0.
Set bits to 0.
1: Configure GPIO pin 46, 47, 53, 54 to be
outputs.
25
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