PC87360 Datasheet, PDF (43/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

2.0 Device Architecture and Configuration (Continued)
2.7.5 SuperI/O Configuration 4 Register (SIOCF4)
Location: Index 24h
Type:
Varies per bit
Bit
Name
Reset
7
6
Pin 127
Function
Select
0
0
5
4
Pins 125,126 PIns 117-124
Function Function
Select
Select
0
0
3
2
Pin 71
Function
Select
0
0
Bit
Description
7-6 Pin 127 Function Select. This is a R/W bit.
Bits
7 6 P* Function
000
010
100
XX1
GPIO32 (default)
P16
IRSL1
PIRQ15
5 Pins 125,126 Function Select. This is a RO bit.
Bits
5 P* Function
0 0 GPIO30,31 (default)
1 0 Reserved
X 1 PIRQ12,14
4 Pins 117-124 Function Select. This is a RO bit.
Bits
4 P* Function
0 0 GPIO20-27 (default)
1 0 Reserved
X 1 PIRQ3-7,9-11
3-2 Pin 71 Function Select. This is a R/W bit.
Bits
3 2 Function
0 0 GPIO17 (default)
0 1 DR1
1 0 IRSL3
1 1 Reserved
1-0 Pin 69 Function Select. This is a R/W bit.
Bits
1 0 Function
0 0 GPIO16 (default)
0 1 MTR1
1 0 IRSL2
1 1 Reserved
* Bit 6, Pins 117-127 Select PIRQ, of the SIOCF1 register
1
0
Pin 69
Function
Select
0
0
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