PC87360 Datasheet, PDF (121/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.4.4 GPIO Data Out Register (GPDO)
Location: Device specific
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Data Out
1
1
1
1
1
1
1
1
Bit
Description
7
6
Data Out. Bits 7-0 correspond to pins 7-0 respectively. The value of each bit determines the value driven on the
5 _{corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the}
4
bit is locked by the GPCFG register Lock bit. Reading the bit returns its value, regardless of the pin value and
configuration.
3 _{0: Corresponding pin driven to low when output enabled}
2 ^{1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when}
output enabled
1
0
6.4.5 GPIO Data In Register (GPDI)
Location: Device specific
Type:
RO
Bit
Name
Reset
7
6
5
4
3
2
1
0
Data In
X
X
X
X
X
X
X
X
Bit
Description
7
6
5
Data In. Bits 7-0 correspond to pins 7-0 respectively. Reading each bit returns the value of the corresponding
4 GPIO pin, regardless of the pin configuration and the GPDO register value. Write is ignored.
3 ^{0: Corresponding pin level low}
1: Corresponding pin level high
2
1
0
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