PC87360 Datasheet, PDF (31/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

2.0 Device Architecture and Configuration (Continued)
2.2.2 Banked Logical Device Registers Structure
Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks,
where each bank holds the standard configuration registers of the corresponding logical device. Table 6 shows the LDN
values of the PC87360 functional blocks.
Figure 2 shows the structure of the standard configuration register file. The SuperI/O control and configuration registers are
not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and
device configuration registers are duplicated over banks for logical devices. Therefore, accessing a specific register in a
specific bank is performed by two dimensional indexing, where the LDN register selects the bank (or logical device) and the
Index register selects the register within the bank. Accessing the Data register while the Index register holds a value of 30h
or higher results in a physical access to the Logical Device Configuration registers currently pointed to by the Index register,
within the logical device currently selected by the LDN register.
07h Logical Device Number Register
20h _{SuperI/O Configuration Registers}
2Fh
30h ^{Logical Device Control Register}
60h
63h
Standard Logical Device
70h
71h
Configuration Registers
74h
75h
F0h
Special (Vendor-defined)
Logical Device
FEh
Configuration Registers
Bank Select
Banks
(One per Logical Device)
Figure 2. Structure of the Standard Configuration Register File
Table 6. Logical Device Number (LDN) Assignments
LDN
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
Functional Block
Floppy Disk Controller (FDC)
Parallel Port (PP)
Serial Port 2 with IR (SP2)
Serial Port 1 (SP1)
System Wake-Up Control (SWC)
Keyboard and Mouse Controller (KBC) - Mouse interface
Keyboard and Mouse Controller (KBC) - Keyboard interface
General-Purpose I/O (GPIO) Ports
ACCESS.bus Interface (ACB)
Fan Speed Control and Monitor (FSCM)
WATCHDOG Timer (WDT)
Write accesses to unimplemented registers (i.e. accessing the Data register while the Index register points to a non-existing
register), are ignored and read returns 00h on all addresses except for 74h and 75h (DMA configuration registers) which
returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.
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