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| PC87360 Datasheet, PDF (105/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support | |||
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3.0 System Wake-Up Control (SWC) (Continued)
3.5 SWC REGISTER BITMAP
Table 40. Banks 0 and 1 - The Common Register Bitmap
Register
Bits
Offset Mnemonic
00h WK_STS0
7
Module
IRQ Event
Status
6
Software
Event
Status
01h WK_STS1
GPIE7
Event
Status
GPIE6
Event
Status
Module Software
02h WK_EN0 IRQ Event Event
Enable Enable
03h WK_EN1
GPIE7
Event
Enable
GPIE6
Event
Enable
04h WK_CFG
05h-07h
08h SB_GPDO0
09h SB_GPDI0
0Ah-12h
Reserved
5
4
3
2
GPIO
Event
Status
CEIR
Event
Status
Mouse
Event
Status
KBD
Event
Status
GPIE5
Event
Status
GPIE4/
RING
Event
Status
GPIE3
Event
Status
GPIE2
Event
Status
GPIO
Event
Enable
CEIR
Event
Enable
Mouse
Event
Enable
KBD
Event
Enable
GPIE5
Event
Enable
GPIE4/
RING
Event
Enable
GPIE3
Event
Enable
GPIE2
Event
Enable
Reserved
Swap KBC
Inputs
Reserved
Data Out
Data In
Reserved
1
RI2
Event
Status
0
RI1
Event
Status
GPIE1
Event
Status
GPIE0
Event
Status
RI2
Event
Enable
RI1
Event
Enable
GPIE1
Event
Enable
GPIE0
Event
Enable
Conï¬guration Bank
Select
Table 41. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Conï¬guration and Control Registers Bitmap
Register
Offset Mnemonic
13h PS2CTL
16h
KDSR
17h MDSR
18h-1Fh
PS2KEY0-
PS2KEY7
7
Disable
Parity
Bits
6
5
4
3
2
1
0
Mouse Wake-Up Conï¬guration
Keyboard Wake-Up Conï¬guration
Reserved
Keyboard Data
Mouse Data
Scan Code of Keys 0-7
Table 42. Bank 1 - CEIR Wake-Up Conï¬guration and Control Registers Bitmap
Register
Offset Mnemonic
13h IRWCR
14h
15h IRWAD
16h IRWAM
17h ADSR
7
6
Reserved
Bits
5
4
3
2
CEIR Protocol Select
Select
IRRX2
Input
Invert
IRRXn
Input
Reserved
CEIR Wake-Up Address
CEIR Wake-Up Address Mask
CEIR Address
1
Reserved
0
CEIR
Enable
105
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