PC87360 Datasheet, PDF (122/168 Pages) National Semiconductor (TI) – 128-Pin LPC SuperI/O with Protection and Extensive GPIO Support

6.0 General-Purpose Input/Output (GPIO) Port (Continued)
6.4.6 GPIO Event Enable Register (GPEVEN)
Location: Device specific
Type:
R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Event Enable
0
0
0
0
0
0
0
0
Bit
Description
7
6
5
Event Enable. Bits 7-0 correspond to pins 7-0 respectively. Each bit enables system notification triggering by
4 the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPST register.
3 ^{0: IRQ generation by corresponding GPIO pin masked}
1: IRQ generation by corresponding GPIO pin enabled
2
1
0
6.4.7 GPIO Event Status Register (GPEVST)
Location: Device specific
Type:
R/W1C
Bit
Name
Reset
7
6
5
4
3
2
1
0
Status
0
0
0
0
0
0
0
0
Bit
Description
7
6
Status. Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware
5 _{upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin.}
4
This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However,
the bit may reflect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it
3 ^{to 0.}
2 ^{0: No active edge detected since last cleared}
1: Active edge detected
1
0
www.national.com
122